Method and system for design rule checking enhanced with pattern matching
US8086981B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 10, 2008 |
| Grant date | Dec 27, 2011 |
| Priority date | — |
| Expiry date | Mar 27, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/398
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
According to various embodiments of the invention, systems and methods for design rule checking enhanced with pattern matching is provided, wherein the design rule checker ignores certain patterns of the layout that violate design rules during validation. One embodiment of the invention includes receiving a first layout pattern that containing the original layout of an integrated circuit pattern. The pattern matcher processes the layout pattern and designates certain patterns of the integrated circuit pattern that meet a design waiver. The pattern matcher generates a second layout pattern with the waived patterns marked. The design rule checker subsequently processes the marked layout pattern and validates all but the marked patterns of the second layout pattern against a set of specified design rules. The design rule checker generates a third layout pattern with only the unmarked patterns of the layout being validated against the set of specified design rules.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.