Structure for glitchless clock multiplexer optimized for synchronous and asynchronous clocks
US8086989B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 16, 2008 |
| Grant date | Dec 27, 2011 |
| Priority date | — |
| Expiry date | Jul 16, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A design structure for a circuit for switching clock signals with logic devices using a glitchless clock multiplexer optimized for synchronous and asynchronous clocks. The design structure comprises a circuit having an asynchronous clock group and one or more synchronous clock group(s). The asynchronous group comprises a plurality of high frequency glitchless control (HFGC) blocks for asynchronous clock sources. Each synchronous group comprises a plurality of HFGC blocks for synchronous clock sources. The circuit comprises a multiplexer for receiving delayed input clock signals from HFGC blocks for asynchronous clock sources and from HFGC blocks for synchronous clock sources. A switching latency (period in which no clock pulse appears at the final output of the circuit) from a first input clock signal belonging to a synchronous group to a second input clock signal belonging to the same synchronous group is one clock cycle or less of the second input clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.