Double-gated transistor memory
US8089108B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 28, 2011 |
| Grant date | Jan 3, 2012 |
| Priority date | — |
| Expiry date | Feb 28, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/223
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Memory cells are constructed from double-gated four terminal transistors having independent gate control. DRAM cells may use one, two or three transistors. Single transistor cells are constructed either with or without a bit storage capacitor, and both NAND- and NOR-type Non-Volatile NVRAM cells, as well as Ferroelectric FeRAM cells, are described. For all cells, top gates provide conventional access while independent bottom gates provide control to optimize memory retention for given speed and power parameters as well as to accommodate hardening against radiation. In a single transistor cell without a capacitor, use of the bottom gate allows packing to a density approaching 2 F2. The memory cells are compatible with SOI logic circuitry for use as embedded RAM in SOC applications.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.