Motor drive device and semiconductor integrated circuit device
US8089232B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 25, 2008 |
| Grant date | Jan 3, 2012 |
| Priority date | — |
| Expiry date | Dec 17, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH02P6/187
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
The disclosed invention achieves a significant reduction in the noise and vibration of a brushless motor from a startup up to the number of steady revolutions. To drive the brushless motor from stop up to the number of steady revolutions, when the arithmetic sequencer detects a rise of a clock signal CARYCLK, current control arithmetic is executed. On detecting a fall of the clock signal, the arithmetic sequence determines whether a division control signal DIVCNT has changed. If this signal has changed, soft switch arithmetic is executed. When the division control signal has not changed or after the completion of soft switching arithmetic, the arithmetic sequencer determines whether a rise of a mask signal MASK has occurred during one cycle of the PWM carrier signal CARYCLK. If a rise of the mask signal has not occurred, the operation returns to the first step. If a rise of the mask signal has occurred, PLL control arithmetic is executed, then the operation returns to the first step.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.