Implementing tamper resistant integrated circuit chips
US8089285B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 3, 2009 |
| Grant date | Jan 3, 2012 |
| Priority date | — |
| Expiry date | Jul 3, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/1461
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and tamper resistant circuit for resisting tampering including reverse engineering in a semiconductor chip, and a design structure on which the subject circuit resides are provided. A sensing device for detecting a chip tampering state is formed with the semiconductor chip including the circuitry to be protected. A tamper resistant control signal generator is coupled to the sensing unit for generating a tamper resistant control signal responsive to a detected chip tampering state. A functional operation inhibit circuit is coupled to the tamper resistant control signal generator for inhibiting functional operation of the circuitry to be protected responsive to the tamper resistant control signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.