Flat panel display apparatus
US8089428B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Oct 24, 2006 |
| Grant date | Jan 3, 2012 |
| Priority date | — |
| Expiry date | Aug 20, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2330/02
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
In an image display apparatus using an FED or an organic EL element, image display that is high in illumination uniformity and high in image quality can be performed. A display element with a matrix structure which conducts linear sequential driving which determines the luminance by a current is used, a threshold voltage of a cathode line immediately before one select period has been terminated where a control electrode line is sequentially driven is measured by a threshold voltage measuring section, the measured threshold voltage is recorded for each of the pixels, and a driving signal at the time of selecting the pixel is corrected by using the value of the recorded threshold voltage, to thereby control electric charge that is emitted from a cathode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.