Nonvolatile semiconductor memory device, and reading method, writing method and erasing method of nonvolatile semiconductor memory device
US8089808B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 27, 2009 |
| Grant date | Jan 3, 2012 |
| Priority date | — |
| Expiry date | Sep 10, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/856
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A nonvolatile semiconductor memory including a memory cell array of memory cells arranged in a matrix, each of which includes a selective transistor and a memory cell transistor; the first column decoder for controlling the potentials of the bit lines and the source lines; the first row decoder for controlling the potential of the first word lines; the second row decoder for controlling the potential of the second word lines; and the second column decoder. The first column decoder includes a circuit whose withstand voltage is lower than the first row decoder and the second column decoder, and the second row decoder includes a circuit whose withstand voltage is lower than the first row decoder and the second column decoder.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.