Method and system of providing a high speed Tomlinson-Harashima Precoder
US8090013B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 6, 2008 |
| Grant date | Jan 3, 2012 |
| Priority date | — |
| Expiry date | Oct 30, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/4975
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Herein described are at least a method and a system for implementing a high speed Tomlinson-Harashima Precoder. The method comprises using an L-tap transpose configuration of a Tomlinson-Harashima Precoder and processing a first discrete time sampled sequence using said L coefficients and L state variables by clocking the L-tap Tomlinson-Harashima Precoder using a clock signal wherein the clock signal has a clock rate equal to one half the symbol rate of the discrete time sampled sequence. In a representative embodiment, an L-tap Tomlinson-Harashima Precoder comprises a single integrated circuit chip, wherein the integrated circuit chip comprises at least one circuitry for processing a discrete time sampled sequence using L coefficients and L state variables by way of clocking the discrete time sampled sequence using a clock signal having a clock rate that is one half the symbol rate of the discrete time sampled sequence.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.