Multiprocessor system, system board, and cache replacement request handling method
US8090912B2 · kind B2 · utility
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9Claims
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Key dates
| Filing date | Apr 24, 2007 |
| Grant date | Jan 3, 2012 |
| Priority date | — |
| Expiry date | Nov 4, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0833
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A request issued by the CPU is output from the local arbiter by way of the CPU bus and the CPU-issued request queue. The cache replacement request loop-back circuit determines at the loop-back determination circuit whether the outputted request is a cache replacement request or not. A request other than a cache replacement request is output onto the local bus. A cache replacement request is output to the selector and sent to the request handling section when there is no valid request on the global bus.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.