Processing device, computer system, and mobile apparatus
US8090921B2 · kind B2 · utility
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3References
14Claims
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Assignee
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Key dates
| Filing date | Sep 6, 2007 |
| Grant date | Jan 3, 2012 |
| Priority date | — |
| Expiry date | Oct 28, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0842
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processing device included on a single chip includes processors capable of executing tasks in parallel and a cache memory shared by the processors, wherein the cache memory includes single-port memories and read data selection units, each of the single-port memories have one data output port, and each of the read data selection units is in a one-to-one association with each of the processors and selects a single-port memory which stores data to be read to a associated processor, from among the single-port memories.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.