Generating clock signals for coupled ASIC chips in processor interface with X and Y logic operable in functional and scanning modes

US8090929B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Jeffrey A. Magee · Poughkeepsie, US
• Timothy G. McNamara · Fishkill, US
• Walter Niklaus · Stuttgart, DE
• Scott Barnett Swaney · Catskill, US
• Tobias Webel · Eppelheim, DE

Key dates

• Filing date: Sep 24, 2008
• Grant date: Jan 3, 2012
• Expiry date: May 21, 2030

Classification

• Technology area (CPC G): Physics
• CPC primary: G01R31/318558
• WIPO field: Measurement
• WIPO sector: Instruments

Abstract

A digital system and method of operating the same. The system comprises a processor chip including a first elastic interface domain, wherein the first elastic interface domain comprises a first processor X logic and a first processor Y logic, wherein the first processor X and Y logic comprise first X and Y latches, respectively; and a first ASIC chip electrically coupled to the processor chip, wherein the first processor X and Y logics are configured to be simultaneously in a functional mode, wherein the first processor X logic is configured to switch from the functional mode to a scanning mode while the first processor Y logic remains in the functional mode, and wherein in response to the first processor Y logic being in the functional mode, the first processor Y logic is configured to generate a first reference ASIC clock signal to the first ASIC chip.