Communication bus with hidden pre-fetch registers
US8090932B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 1, 2010 |
| Grant date | Jan 3, 2012 |
| Priority date | — |
| Expiry date | Nov 1, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F3/0676
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system-on-chip including a processor, a control module, a first plurality of data registers, a second plurality of data registers, a plurality of address registers, and a first control module. The first plurality of data registers are configured to store data. The processor is configured to respectively write addresses corresponding to selected ones of the first plurality of data registers in the plurality of address registers. The second plurality of data registers are configured to receive data from the selected ones of the first plurality of data registers. In response to a request from the processor for a first address, the first control module is configured to provide data to the processor from the second plurality of data registers in response to the first address matching an address stored in the plurality of address registers, and otherwise provide data to the processor from the first plurality of data registers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.