Error correction for digital systems
US8090976B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 29, 2007 |
| Grant date | Jan 3, 2012 |
| Priority date | — |
| Expiry date | Jun 22, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/09
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
An interface system is provided between a source component (210) and a destination component (220) having multiple parallel lines for transmitting data or parity bits (231-234, 251-253) and one or more spare lines (241-243). An error detection means (222) identifies one or more faulty lines. A mapping means (228) re-routes data or parity from a faulty line to a spare line. A communication link (208) is provided for communicating the re-routing between the source component (210) and the destination component (220). The error detection and mapping can be repeated to detect and re-route sequential multiple-bit line errors using additional spare lines (241-243).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.