Multiple-capture DFT system to reduce peak capture power during self-test or scan test

US8091002B2 · kind B2 · utility

Assignee

• SYNTEST TECHNOLOGIES, INC. · US

Inventors

• Laung-Terng Wang · Sunnyvale, US
• Shianling Wu · Princeton Junction, US
• Zhigang Jiang · San Jose, US
• Jinsong Liu · Shanghai, CN
• Hao-Jan Chao · Taoyuan, TW
• Lizhen Yu · Shanghai, CN
• Feifei Zhao · Shanghai, CN
• Fangfang Li · Beijing, CN
• Jianping Yan · Milpitas, US

Key dates

• Filing date: Jun 9, 2010
• Grant date: Jan 3, 2012
• Expiry date: Jun 9, 2030

Classification

• Technology area (CPC G): Physics
• CPC primary: G01R31/318594
• WIPO field: Measurement
• WIPO sector: Instruments

Abstract

A method for providing ordered capture clocks to detect or locate faults within N clock domains and faults crossing any two clock domains in an integrated circuit or circuit assembly in scan-test or self-test mode, where N>1, each clock domain having one capture clock and a plurality of scan cells, each capture clock comprising a plurality of capture clock pulses; said method comprising: (a) generating and shifting-in N test stimuli to all said scan cells within said N clock domains in said integrated circuit or circuit assembly during a shift-in operation; (b) applying an ordered sequence of capture clocks to all said scan cells within said N clock domains, the ordered sequence of capture clocks comprising at least a plurality of capture clock pulses from two or more selected capture clocks placed in a sequential order such that all clock domains are never triggered simultaneously during a capture operation; and (c) analyzing output responses of all said scan cells to locate any faults therein.