Information flow enforcement for RISC-style assembly code in the presence of timing-related covert channels and multi-threading
US8091128B2 · kind B2 · utility
4Cited by
2References
32Claims
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Key dates
| Filing date | Aug 16, 2007 |
| Grant date | Jan 3, 2012 |
| Priority date | — |
| Expiry date | Feb 25, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F21/556
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus is disclosed for performing information flow enforcement for assembly code. In one embodiment, the method comprises receiving assembly code having timing annotations with type information that enforce information flow with respect to one or more of timing-related covert and concurrent channels when statically checked as to whether the code is in violation of a security policy and performing verification with respect to information flow for the assembly code based on a security policy.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.