Non-volatile semiconductor memory device and depletion-type MOS transistor
US8093664B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 26, 2009 |
| Grant date | Jan 10, 2012 |
| Priority date | — |
| Expiry date | Jun 26, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B41/43
Abstract
A peripheral circuit includes at least a first transistor. The first transistor comprises a gate electrode formed on a surface of a semiconductor layer via a gate insulating film. A channel region of a first conductivity type having a first impurity concentration is formed on a surface of the semiconductor layer directly below and in the vicinity of the gate electrode. A source-drain diffusion region of the first conductivity type is formed on the surface of the semiconductor layer to sandwich the gate electrode and has a second impurity concentration greater than the first impurity concentration. An overlapping region of the first conductivity type is formed on the surface of the semiconductor layer directly below the gate electrode where the channel region and the source-drain diffusion region overlap. The overlapping region has a third impurity concentration greater than the second impurity concentration.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.