System for noise reduction in circuits
US8093765B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | May 28, 2010 |
| Grant date | Jan 10, 2012 |
| Priority date | — |
| Expiry date | May 28, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/00392
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Disclosed is an improved noise reducing apparatus using an anti-circuit, including a digital logic circuit and a digital anti-circuit corresponding to the digital logic circuit. The digital anti-circuit functions to cancel noise generated by the digital logic circuit. The anti-circuit includes logic to generate a similar number of switching edges as the logic circuit, where the anti-circuit edges are in the opposite direction as the logic circuit. The anti-circuit may have a circuit structure close to that of the noisy circuit, or can be formed of components different in structure but generating an output pattern similar to (and opposite from) the noisy circuit. In some embodiments, the differently structured components can include a state machine coupled to a memory or look-up-table.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.