Analog-to-digital converter
US8094056B2 · kind B2 · utility
11Cited by
20References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 15, 2008 |
| Grant date | Jan 10, 2012 |
| Priority date | — |
| Expiry date | Sep 15, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/44
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A lookahead pipelined ADC architecture uses open-loop residue amplifiers with calibration. This approach is able to achieve a high-speed, high-accuracy ADC with reduced power consumption. In one aspect, an ADC pipeline unit includes a plurality of lookahead pipeline stages (i.e., an ADC lookahead pipeline) coupled to a calibration unit. The ADC lookahead pipeline uses open-loop residue amplifiers. The calibration unit compensates for non-linearity in the open-loop amplifiers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.