Digital column gain mismatch correction for 4T CMOS imaging systems-on-chip
US8094215B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 2, 2008 |
| Grant date | Jan 10, 2012 |
| Priority date | — |
| Expiry date | May 6, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N25/78
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods are provided that facilitate mitigating column gain mismatch in a CMOS imaging System-on-Chip (iSoC) sensor. Tunable voltages that mimic presence of photo-charge can be provided to test pixels in one or more rows of a pixel array. Moreover, column-specific digital gain corrections can be calibrated based upon input data received from the test pixels. During calibration, actual data can be compared to a target expected to be obtained via an analog readout architecture. The calibrated, column-specific digital gain corrections can be utilized to correct for column gain mismatch to yield output data. Further, correction values corresponding to the column-specific digital gain corrections can be retained in and retrieved from memory. The correction values, for example, can be a function of a scaling parameter that is tuned to match an available memory dynamic to a range of uncorrected gain mismatch.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.