Nonvolatile semiconductor memory device
US8094498B2 · kind B2 · utility
1Cited by
32References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 2, 2010 |
| Grant date | Jan 10, 2012 |
| Priority date | — |
| Expiry date | Aug 28, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B69/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a nonvolatile semiconductor memory device storing data by accumulating charges in a floating gate, memory units, each of which includes a first MOS transistor as a read device, a bit cell composed of a first capacitor as a capacitance coupling device and a second capacitor as an erase device, and a decode device including a second MOS transistor and a third MOS transistor, are arranged in array. This attains nonvolatile memory capable of bit by bit selective erase arranged in array to thus reduce the core area remarkably.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.