Software parameterizable control blocks for use in physical layer processing
US8094653B2 · kind B2 · utility
5Cited by
9References
13Claims
0Family size
Assignee
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Key dates
| Filing date | Feb 23, 2009 |
| Grant date | Jan 10, 2012 |
| Priority date | — |
| Expiry date | Jul 5, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04W80/00
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A physical layer transport composite processing system used in a wireless communication system. A plurality of interconnected processing blocks are provided. The blocks are interconnected by a read data bus, a write data bus and a control bus. The blocks include a transport channel processing block, a composite channel processing block and a chip rate processing block. At least two of the blocks are capable of processing data for a plurality of wireless formats. A first set of parameters is programmed into the blocks for a particular wireless mode. The blocks are operated to process data in the particular wireless format mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.