Multi-channel timing recovery system
US8094768B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 21, 2006 |
| Grant date | Jan 10, 2012 |
| Priority date | — |
| Expiry date | Apr 9, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L27/2679
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
The present invention discloses a novel multi-channel timing recovery scheme that utilizes a shared CORDIC to accurately compute the phase for each tone. Then a hardware-based linear combiner module is used to reconstruct the best phase estimate from multiple phase measurements. The firmware monitors the noise variance for the pilot tones and determines the corresponding weight for each tone to ensure that the minimum phase jitter noise is achieved through the linear combiner. Then a hardware-based second-order timing recovery control loop generates the frequency reference signal for VCXO or DCXO. A single sequentially controlled multiplier is used for all multiplications in the control loop.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.