Network delay analysis including parallel delay effects
US8095649B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 1, 2008 |
| Grant date | Jan 10, 2012 |
| Priority date | — |
| Expiry date | Sep 2, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L69/28
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A multi-functional graphical user interface facilitates the analysis and assessment of application delays, including delays that occur on multiple paths. A trace file of an application's network events is processed to categorize the causes of delays incurred in the propagation and processing of these events. The system identifies the amount of delay (‘component delay’) that can be eliminated by eliminating each of the components of delay individually, as well as the amount of delay (‘parallel delay’) that can be eliminated by eliminating combinations of the delay components. A user interface displays the amount of reduction that can be achieved by eliminating each component delay individually and the amount of reduction that can be achieved by eliminating combinations of the individual component delays. To facilitate the analysis and assessment of these potential reductions, the interface allows the user to ‘drill down’ to view the individual delay components contained in each combination forming the parallel delays. In this manner, the user is provided a view of each of the delay components that would need to be addressed, either individually or in combination, to improve the over…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.