High speed memory access in an embedded system
US8095702B2 · kind B2 · utility
1Cited by
2References
25Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Mar 19, 2008 |
| Grant date | Jan 10, 2012 |
| Priority date | — |
| Expiry date | Oct 5, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/253
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Data is processed in an embedded system by writing data read from a peripheral device in response to an event to memory external to the embedded system. The data or a portion of the data is copied to memory internal to the embedded system. Which portion of the data is stored in both the external memory and the internal memory is tracked. The copied data is retrieved from the internal memory by a processor included in the embedded system. The processor has one or more caches logically and physically separated from the internal memory. The processor uses the copied data it retrieved to begin servicing the event.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.