Patent · US Active

Debugging for multiple errors in a microprocessor environment

US8095821B2 · kind B2 · utility

3Cited by

7References

20Claims

0Family size

Assignee

International Business Machines Corporation · US

Inventors

Ulrich Mayer · Weißenhorn, DE
Timothy J. Slegel · Staatsburg, US
Chung-Lung K. Shum · Wappingers Falls, US
Frank Lehnert · Weil im Schönbuch, DE
Guenter Gerwig · Simmozheim, DE

Key dates

Filing date	Mar 17, 2009
Grant date	Jan 10, 2012
Priority date	—
Expiry date	Aug 19, 2029

Classification

Technology area (CPC G)Physics
CPC primaryG06F11/076
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A new method and apparatus have been taught for storing error information used for debugging as generated by the initial and subsequent error occurrences. In this invention, a register with several bit ranges is used to store error information. The first bit-range is allocated to the initial error information. If the total number of the errors exceeds the capacity of the register, the last error is kept in a last bit-range. This way, precious initial error information (as well as the last error information) will be available for debugging.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.