Error correction method with instruction level rollback
US8095825B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 16, 2007 |
| Grant date | Jan 10, 2012 |
| Priority date | — |
| Expiry date | Oct 9, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1407
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
This method is an error correction method such that, when an error is detected in a CPU with pipeline structure, a content of a register file is restored by a delayed register file which holds an execute completion state of an [Instruction N] correctly executed before this error, and a rollback control that re-executes an instruction from the [Instruction N+1] which is the next instruction of the [Instruction N] is performed. The method collects a parity check result of arbitrary Flip-Flops existing inside the CPU, and detects an error. As a result, the content of the register file is restored into the instruction execute completion state preceding to the instruction range likely to malfunction by the error, and the instruction can be roll backed from the beginning of the instruction range likely having malfunctioned by the error.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.