Reliability evaluation and system fail warning methods using on chip parametric monitors
US8095907B2 · kind B2 · utility
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10Claims
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Key dates
| Filing date | Oct 19, 2007 |
| Grant date | Jan 10, 2012 |
| Priority date | — |
| Expiry date | Oct 13, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/2894
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method of reliability evaluation and system fail warning using on chip parametric monitors. The method includes determining impact of parametric variation on reliability by identifying key parametric questions to be answered by stress, identifying parametric macros for each parameter, and identifying layout sensitive areas of evaluation. The process can also include a set of parametric macros in one of a test site or a product to be stressed, testing the set of parametric macros prior to start of stress and at each stress read out, and setting life time parameter profile for technology.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.