Post-pass binary adaptation for software-based speculative precomputation
US8095920B2 · kind B2 · utility
6Cited by
5References
47Claims
0Family size
Assignee
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Key dates
| Filing date | Sep 17, 2002 |
| Grant date | Jan 10, 2012 |
| Priority date | — |
| Expiry date | Jun 11, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F8/4442
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The latencies associated with cache misses or other long-latency instructions in a main thread are decreased through the use of a simultaneous helper thread. The helper thread is a speculative prefetch thread to perform a memory prefetch for the main thread. The instructions for the helper thread are dynamically incorporated into the main thread binary during post-pass operation of a compiler.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.