Modifiable gate stack memory element
US8097872B2 · kind B2 · utility
4Cited by
11References
20Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Feb 20, 2007 |
| Grant date | Jan 17, 2012 |
| Priority date | — |
| Expiry date | Mar 29, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/0413
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus and method for storing information are provided, including using an integrated circuit including a transistor having a channel, a gate oxide layer, a gate electrode, and a modifiable gate stack layer. To store information, the on-resistance of the transistor is changed by causing a non-charge-storage based physical change in the modifiable gate stack layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.