Method and apparatus for standby voltage offset cancellation
US8098087B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 5, 2007 |
| Grant date | Jan 17, 2012 |
| Priority date | — |
| Expiry date | Oct 20, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/249
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A method and apparatus is provided for standby voltage offset cancellation at inputs to a comparator within a receiver channel. Each of a first comparator input and second comparator input is isolated from an input signal such that each of the first and second comparator inputs attains a respective standby voltage level. A voltage level on one of the first and second comparator inputs is incrementally changed, while the output signal of the comparator is monitored. Upon detecting a state transition in the output signal of the comparator, the incremental changing of the voltage level on the one comparator input is stopped at a final voltage level setting. The final voltage level setting is stored in a computer memory for reference in setting of the voltage level at the one comparator input so as to compensate for the standby voltage offset at the inputs to the comparator.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.