System and method for instruction latency reduction in graphics processing
US8098251B2 · kind B2 · utility
3Cited by
4References
50Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Feb 22, 2008 |
| Grant date | Jan 17, 2012 |
| Priority date | — |
| Expiry date | Nov 12, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F8/445
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system, method and apparatus are disclosed, in which an instruction scheduler of a compiler, e.g., a shader compiler, reduces instruction latency based on a determined instruction distance between a dependent predecessor and successor instructions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.