Phase management for interleaved power factor correction
US8098505B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 20, 2009 |
| Grant date | Jan 17, 2012 |
| Priority date | — |
| Expiry date | Feb 8, 2030 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02B70/10
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
An interleaved power factor correction (PFC) circuit includes phase management to control shedding and adding of channels. The channels may be voltage (e.g., boost) converters connected in parallel. The interleaved PFC circuit can have a first channel and a second channel that operate out of phase of each other to provide input power to a load. In a two phase interleaved PFC circuit, the first and second channels operate 180 degrees out of phase. A channel may be shed or added depending on load conditions. The phase management can be configured to add or remove a channel only when the AC line input to the interleaved PFC circuit crosses zero.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.