Semiconductor memory device and manufacturing method thereof
US8098527B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 30, 2009 |
| Grant date | Jan 17, 2012 |
| Priority date | — |
| Expiry date | May 15, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B41/30
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device includes a semiconductor substrate; a memory cell array on the semiconductor substrate, the memory cell array comprising a plurality of memory cells capable of electrically storing data; a sense amplifier configured to detect the data stored in at least one of the memory cells; a cell source driver electrically connected to source side terminals of the memory cells and configured to supply a source potential to at least one of the source side terminals of the memory cells; a first wiring configured to electrically connect between at least one of the source side terminals of the memory cells and the cell source driver; and a second wiring formed in a same wiring layer as the first wiring, the second wiring being insulated from the first wiring and being electrically connected to the sense amplifier, wherein the first wiring and the second wiring have a plurality of through holes provided at a predetermined interval.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.