Patent · US Active

Hybrid single and dual channel DDR interface scheme by interleaving address/control signals during dual channel operation

US8098539B2 · kind B2 · utility

7Cited by

1References

37Claims

0Family size

Assignee

QUALCOMM Incorporated · US

Inventors

Raghu Sankuratri · San Diego, US
Michael Drop · San Diego, US
Jian Mao · Beijing, CN

Key dates

Filing date	Aug 26, 2009
Grant date	Jan 17, 2012
Priority date	—
Expiry date	Jan 21, 2030

Classification

Technology area (CPC G)Physics
CPC primaryG06F13/1684
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A memory structure is described. In one embodiment, the memory structure comprises a memory controller configured to receive a clock signal and to be coupled to a plurality of memory modules via a single address/control bus. The memory controller couples to each of the plurality of memory modules via a separate chip select signal for each memory module. The memory controller issues commands across the address/control bus to the memory modules in an interleaved fashion in accordance with the timing supplied by the clock. During a waiting period after issuance of a command to one memory module, the memory controller can issue commands to a different memory module.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.