Shared memory system for a tightly-coupled multiprocessor
US8099561B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 9, 2008 |
| Grant date | Jan 17, 2012 |
| Priority date | — |
| Expiry date | Mar 11, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4247
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A shared memory system for a multicore computer system utilizing an interconnection network that furnishes tens of processing cores or more with the ability to refer concurrently to random addresses in a shared memory space with efficiency comparable to the typical efficiency achieved when referring to private memories. The network is essentially a lean and light-weight combinational circuit, although it may also contain non-deep pipelining. The network is generally composed of a sub-network for writing and a separate multicasting sub-network for reading, whose topologies are based on multiple logarithmic multistage networks, e.g. Baseline Networks, connected in parallel. The shared memory system computes paths between processing cores and memory banks anew at every clock cycle, without rearrangement. It returns an approval reply to every core whose initiative of accessing memory leads to the successful establishment of a path and is fulfilled, or a rejection reply to every core whose initiative is not fulfilled.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.