Load/store ordering in a threaded out-of-order processor
US8099566B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 15, 2009 |
| Grant date | Jan 17, 2012 |
| Priority date | — |
| Expiry date | Jul 22, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0893
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods for efficient load-store ordering. A processor comprises a store buffer that includes an array. The store buffer dynamically allocates any entry of the array for an out-of-order (o-o-o) issued store instruction independent of a corresponding thread. Circuitry within the store buffer determines a first set of entries of the array entries that have store instructions older in program order than a particular load instruction, wherein the store instructions have a same thread identifier and address as the load instruction. From the first set, the logic locates a single final match entry of the first set corresponding to the youngest store instruction of the first set, which may be used for read-after-write (RAW) hazard detection.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.