Error detection in physical interfaces for point-to-point communications between integrated circuits
US8099648B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 2, 2011 |
| Grant date | Jan 17, 2012 |
| Priority date | — |
| Expiry date | May 2, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2001/0092
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
An apparatus, system and method for detecting errors in a physical interface during the transmission or receipt of data communications between integrated circuits (“ICs”) are disclosed. In one embodiment, a physical interface formed as a first IC on a first substrate portion to detect transmission errors in data exchanged with a second IC formed on a second substrate portion, the physical interface including multiple input ports and output ports, including a first subset of input ports configured to receive in-bound encoded data bits and a first subset of output ports configured to transmit in-bound decoded data bits to the second IC; and one or more error recovery modules coupled between the plurality of input ports and output ports, where a first error recovery module of the one or more error recovery modules is coupled between at least one of the first subset of input ports and at least one of the first subset of output ports.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.