Model based microdevice design layout correction
US8099685B2 · kind B2 · utility
4Cited by
8References
28Claims
0Family size
Assignee
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Key dates
| Filing date | Jul 31, 2008 |
| Grant date | Jan 17, 2012 |
| Priority date | — |
| Expiry date | Feb 1, 2030 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02P90/02
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Shapes neighboring a potential manufacturing fault within a microdevice design layout are identified. Models are employed to determine the affect of the shapes upon the potential manufacturing fault. Possible adjustments to the shapes are modeled. The possible adjustments facilitating resolution of the potential manufacturing fault.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.