Hardware logic verification support apparatus, verification support method and computer product
US8099697B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 15, 2009 |
| Grant date | Jan 17, 2012 |
| Priority date | — |
| Expiry date | Mar 24, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/331
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer-readable recording medium stores therein a verification support program that causes a computer to execute receiving a hardware description of a combinational circuit to be verified; extracting, from the hardware description, a conditional branch description expressing conditional branch processing; identifying, from among conditional branch descriptions extracted at the extracting of a conditional branch description and based on a description sequence in the hardware description, a combination of conditional branch descriptions having a hierarchical relation; extracting, from among combinations of conditional branch descriptions identified at the identifying, a combination having a potential to satisfy a specified condition; creating a simulation program that causes the specified condition for the conditional branch descriptions included in the combination extracted at the extracting of the combination to be satisfied; and outputting, as assertion information of the combinational circuit, the simulation program created for each combination at the creating.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.