Efficient chip routing method and apparatus for integrated circuit blocks with multiple connections
US8099701B2 · kind B2 · utility
1Cited by
6References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 27, 2009 |
| Grant date | Jan 17, 2012 |
| Priority date | — |
| Expiry date | Apr 11, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/392
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and apparatuses are disclosed for improving the speed of chip routing for integrated circuit blocks with multiple connections. In some embodiments, the method may include creating a layout abstract for a first block and a second block of the integrated circuit, where the first and second blocks are coupled together via a plurality of connections. The method may further include determining whether the number of connections in the plurality exceeds a threshold, and in the event that the number of connections exceeds the predetermined threshold, representing a first subset of the plurality as a first logical connection.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.