Skew exception detection
US8099732B2 · kind B2 · utility
4Cited by
4References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 17, 2006 |
| Grant date | Jan 17, 2012 |
| Priority date | — |
| Expiry date | Nov 17, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2209/5022
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques are presented for skew exception detection within a parallel processing environment. A potential exception is detected when a highest load of a processor within the parallel processing environment exceeds an average load within the parallel processing environment by a given threshold. The potential exception can become a legitimate exception when it exists for a qualified period or time or when it exists and no qualified period of time is noted. In an embodiment, checks for the potential exception occur and are wholly contained within a given configurable interval.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.