Spacer lithography processes
US8101481B1 · kind B1 · utility
2Cited by
0References
8Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Feb 25, 2008 |
| Grant date | Jan 24, 2012 |
| Priority date | — |
| Expiry date | Apr 22, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/01
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A spacer lithography process for creating negative features such as, for example, cut-lines, or trenches, and holes is provided. The negative spacer lithography process may be utilized along with positive spacer lithography to fabricate electronic devices or the like. In one embodiment, a process is provided for fabricating a 6-transistor Static Random-Access Memory (SRAM) cell or arrays of 6-transistor SRAM cells using only, or at least primarily, positive and negative spacer lithography.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.