Via design for flux residue mitigation
US8102057B2 · kind B2 · utility
2Cited by
12References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 27, 2006 |
| Grant date | Jan 24, 2012 |
| Priority date | — |
| Expiry date | Jan 27, 2030 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T428/24273
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
Provided is an electrically conductive via for reducing flux residue. The via has a first aperture having a first diameter size. The via further has a second aperture having a second diameter size. A chamber is disposed between the first aperture and the second aperture, the chamber having a third diameter size. At least one of the diameters being of a different dimension than the other two. In addition, the via may also provide improved test point access in addition to reducing flux residue.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.