Digital phase locked loop
US8102197B1 · kind B1 · utility
3Cited by
3References
20Claims
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Key dates
| Filing date | Oct 28, 2010 |
| Grant date | Jan 24, 2012 |
| Priority date | — |
| Expiry date | Oct 28, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R23/15
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
An adaptive digital phase locked loop comprises: a digital configurable phase detector for receiving a reference signal and a feedback signal and for generating a detection signal indicative of a phase/frequency difference between the reference signal and the feedback signal; a configurable digital loop filter for filtering the DPFD detection signal; a digital locking monitor for monitoring polarity transitions of the detection signal and adaptively switching the locking modes and DCO tuning resolution; and a DCO for generating the feedback signal as a function of the detection signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.