Processor for executing an AES-type algorithm
US8102997B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 29, 2004 |
| Grant date | Jan 24, 2012 |
| Priority date | — |
| Expiry date | May 24, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2209/122
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A processor for executing a Rijndeal algorithm which applies a plurality of encryption rounds to a data block array in order to obtain an array of identical size, each round involving a key block array and a data block substitution table, wherein said processor comprises: a first input register (102) containing an input data block column; an output register (111) containing an output data block column or an intermediate block column; a second input register (101) containing a key block column or the intermediate data blocks; a block substitution element (104) receiving the data one block at a time following the selection (103) thereof in the first register and providing, for each block, a column of blocks; an element (109) applying a cyclic permutation to the substitution circuit column blocks; and an Exclusive-OR combination element (110) combining the permutation circuit column blocks with the content of the second register, the result of said combination being loaded into the output register.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.