Trainable hierarchical memory system and method
US8103603B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 31, 2010 |
| Grant date | Jan 24, 2012 |
| Priority date | — |
| Expiry date | Jun 16, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06N3/0895
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Memory networks and methods are provided. Machine intelligence is achieved by a plurality of linked processor units in which child modules receive input data. The input data are processed to identify patterns and/or sequences. Data regarding the observed patterns and/or sequences are passed to a parent module which may receive as inputs data from one or more child modules. the parent module examines its input data for patterns and/or sequences and then provides feedback to the child module or modules regarding the parent-level patterns that correlate with the child-level patterns. These systems and methods are extensible to large networks of interconnected processor modules.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.