Flash memory device with wear-leveling mechanism and controlling method thereof
US8103821B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 3, 2009 |
| Grant date | Jan 24, 2012 |
| Priority date | — |
| Expiry date | Jun 14, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/7211
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A flash memory device with a wear-leveling mechanism includes at least one flash memory, a hot list, a bitmap, a source pointer, and a controller. The controller obtains a physical memory block with high erase count through the hot list, an erase count of the physical memory block, and an overall average erase count of the flash memory device. The controller further finds out a physical memory block which stores static data through managing the bitmap and the source pointer. The controller moves the static data to the physical memory block with high erase count, and releases the physical memory block which stores the static data to avoid the physical memory block with high erase count being worn down increasingly more seriously.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.