Efficient parallel floating point exception handling in a processor
US8103858B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 30, 2008 |
| Grant date | Jan 24, 2012 |
| Priority date | — |
| Expiry date | Jun 18, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/30036
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and apparatus are disclosed for handling floating point exceptions in a processor that executes single-instruction multiple-data (SIMD) instructions. In one embodiment a numerical exception is identified for a SIMD floating point operation and SIMD micro-operations are initiated to generate two packed partial results of a packed result for the SIMD floating point operation. A SIMD denormalization micro-operation is initiated to combine the two packed partial results and to denormalize one or more elements of the combined packed partial results to generate a packed result for the SIMD floating point operation having one or more denormal elements. Flags are set and stored with packed partial results to identify denormal elements. In one embodiment a SIMD normalization micro-operation is initiated to generate a normalized pseudo internal floating point representation prior to the SIMD floating point operation when it uses multiplication.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.