Method and system for presenting an interrupt request to processors executing in lock step
US8103861B2 · kind B2 · utility
3Cited by
4References
6Claims
0Family size
Assignee
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Key dates
| Filing date | Feb 3, 2006 |
| Grant date | Jan 24, 2012 |
| Priority date | — |
| Expiry date | Apr 7, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/52
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and system of presenting an interrupt request to processors executing in lock step. At least some of the illustrative embodiments are computer systems comprising a first processor configured to execute a program, a second processor configured to execute a duplicate copy of the program in lock step with the first processor, and a logic device coupled to the processors. The logic device is configured to present an interrupt request to the processors when the processors are at substantially the same computational point in the program.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.