High speed memory error detection and correction using interleaved (8,4) LBCs
US8103934B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 21, 2007 |
| Grant date | Jan 24, 2012 |
| Priority date | — |
| Expiry date | Nov 22, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1012
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Methods and systems are disclosed for the detection and correction of memory errors using code words with a quantity, divisible by 4, of data bits, with an equal quantity of check bits, and having the check bits and data bits interleaved. Upon execution of a memory write instruction, a processor may send a memory word to a check bit generator that generates the check bits before the code word is written to a memory unit. Upon a signal from the processor that a memory read is requested, the memory unit may send a stored code word to a syndrome bit generator to generate a syndrome vector. The syndrome vector may then be sent to a correction bit generator and an uncorrectable error detector. These units may send corrected bits and an uncorrectable error signal, respectively, to the processor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.